For decades, the computing industry has followed a simple formula: make transistors smaller and pack more of them onto a chip. That strategy fueled the extraordinary rise in computing power predicted by Moore’s law. But as components approach atomic scales, engineers are increasingly running into the physical limits of silicon and the effects of quantum mechanics.
Many researchers believe the next major advance will come not from shrinking devices further, but from building upward.
A team led by University of Illinois Grainger College of Engineering materials science and engineering professor Qing Cao has demonstrated a new method for stacking multiple layers of silicon electronics directly on top of one another. The approach could dramatically increase computing density, improve performance, and reduce energy consumption while extending the progress that has driven the semiconductor industry for more than half a century.
“Take something as simple as static random-access memory, which is universal in CPUs and GPUs. Today it takes six microelectronic devices called transistors on a single plane to store one bit of information. With vertical integration, you can distribute them across multiple layers. It’s like replacing a sprawling suburb with high-rises: you get the same functionality, but the spatial footprint is reduced while making communication between layers faster and more efficient,” Cao explained.
The researchers report that their process achieves device yields of 98‒100% while using standard single-crystalline silicon, the semiconductor material that underpins modern electronics. The results suggest the technique could eventually be adopted by commercial chip manufacturers.
“Vertical integration is already starting to make its way into commercial devices, particularly in specialized AI hardware, but monolithic integration is what unlocks the full promise of 3D chips,” Cao said. “For the first time, we have met the thermal budget of monolithic 3D integration using standard single-crystalline silicon and delivered unprecedented performance.”
The findings were published in Nature, a journal that rarely features silicon microelectronics research articles.
Why the Semiconductor Industry Is Looking Upward
For roughly 60 years, Moore’s law has guided chip development. The principle predicts that transistor density on integrated circuits will double about every two years, leading to faster and more efficient processors.
That trend has held remarkably well, but it is becoming increasingly difficult to sustain.
“In a sense, we’re hitting a limit imposed by physics,” Cao said. “If you look at the actual size of transistors, they’re not getting smaller, especially in terms of their contacted gate pitch. This is because we’re becoming limited by the intrinsic material properties of silicon and the fundamental rules of quantum mechanics. If we’re going to keep up the trend of increasing processing power of our microprocessors, we have to start thinking beyond just squeezing more devices on a single surface.”
Stacking devices vertically offers an attractive alternative. Instead of continuing to shrink individual transistors, engineers can place multiple layers of circuits on top of one another. This not only creates more room for components but also shortens wiring distances, reducing parasitic capacitance and significantly increasing communication bandwidth between different parts of a chip.
Those advantages are particularly important for artificial intelligence and other data-intensive computing applications.
The Promise of Monolithic 3D Chips
Current commercial 3D chip technologies already use stacking, but they typically involve manufacturing semiconductor devices on separate wafers before bonding them together. Examples include high-bandwidth memory and AMD’s 3D V-Cache technology.
While successful, these methods have limitations. Alignment between layers is relatively coarse, and the vertical connections known as through-silicon vias (TSVs) are comparatively large and sparse.
Monolithic three-dimensional integration takes a different approach. Rather than joining completed wafers, each new device layer is fabricated directly on top of the previous one. This allows much denser vertical connections, smaller distances between layers, and alignment accuracy measured in nanometers.
Researchers have pursued this concept for years because it could increase interlayer connectivity by a factor of 10 to 100 compared with conventional stacking methods.
Solving the Heat Problem
The biggest obstacle to monolithic integration has been temperature.
Producing high-quality crystalline silicon and fabricating high-performance semiconductor devices typically requires temperatures approaching 1,000 degrees Celsius. However, once metal interconnects are already present in a completed circuit layer, such temperatures would destroy them.
“Generally, the industry accepts that once the first layer of circuits is complete, the thermal budget limit for any additional layers is 400 degrees Celsius,” Cao said. “Researchers in both academia and industry have tried to get around this by working with semiconductor materials other than single-crystalline silicon for the upper layers. But the resulting devices all inevitably suffer from issues with performance and reliability.”
Previous efforts have explored alternatives including polycrystalline silicon, amorphous and nanocrystalline metal oxides, carbon nanotubes, and two-dimensional semiconductors. However, those materials often introduce performance limitations or defects that create a mismatch with the silicon transistors in the bottom layer.
Ultrathin Silicon Nanomembranes Enable Low Temperature Manufacturing
The Illinois team developed a process that preserves the advantages of single-crystal silicon while staying well below the thermal limit.
The method begins by creating ultrathin freestanding silicon nanomembranes from a donor wafer. These membranes are then transferred onto a receiving substrate that already contains completed circuitry using a roll laminator. The bonding process requires temperatures of no more than 200 degrees Celsius.
Because the silicon layers retain their crystalline quality, the resulting devices maintain strong performance and reliability while remaining safely within the thermal budget required for monolithic integration.
“Our method is not only easier to implement with lower cost, but it has several advantages over previous approaches to stack silicon wafers,” Cao said. “The membranes we transferred are only 10 nanometers thick or less, compared to the 500 to 700 micrometers thickness of a typical wafer. Because they are thin, these membranes are mechanically flexible to conform to the underlying surface. This conformality helps avoid interfacial defects like voids, which are common when trying to force two rigid wafers together via wafer bonding.”
High Performance With Three Stacked Layers
The researchers also redesigned the transistor architecture.
Traditional transistor manufacturing relies on a process called doping, which introduces impurities into silicon to control electrical behavior. That process usually requires temperatures above 600 degrees Celsius.
To avoid those temperatures, the team used junctionless transistors. In these devices, the silicon is uniformly and heavily doped before the stacking process begins. The extremely thin silicon films still allow effective control by the transistor gate, while the high doping levels help reduce parasitic contact resistance.
Using this strategy, the researchers fabricated three stacked layers containing 625 transistors each. The devices showed strong uniformity and high manufacturing yield.
Their output current densities matched those of conventional silicon transistors fabricated on bulk wafers at much higher temperatures. They also outperformed monolithic devices made from alternative materials by at least a factor of three to four.
The team connected the layers using vertical metal interconnects and successfully demonstrated three-dimensional logic circuits as well as static random-access memory cells.
Toward Commercial Semiconductor Manufacturing
According to Cao, the most significant result may be the scalability of the process.
“But most importantly, we’ve shown that this process is scalable,” Cao said. “You can keep stacking layers beyond the three we demonstrated. And the process will yield high-performing transistors with high yield and low variability. We now have a strong foundation for transferring this technology and demonstrating its immediate promise in an industrial semiconductor foundry.”
The work was carried out through Illinois Grainger Engineering’s Center for Advanced Semiconductor Chips with Accelerated Performance, whose industry partners include IBM, Intel, and the Taiwan Semiconductor Manufacturing Company.
The researchers are now preparing to transfer the technology to an industrial semiconductor foundry, an important step toward bringing true monolithic 3D silicon chips into commercial production.
Additional contributors to the study included Bao Lam, Yung Man Yu, Hyunjun Nam, Hsu-Chih Ni, Shomik Chatterjee, Shaloo Rakheja, and Jian-Min Zhuo.
Funding was provided by the National Science Foundation, industry partners of Illinois Grainger Engineering’s Center for Advanced Semiconductor Chips with Accelerated Performance, and the Silicon Crossroads Microelectronics Commons Hub.
